FIG. 1 shows a prior art display driver circuit 100, for driving a pixel array 102, which includes an array of pixel cells arranged in 768 rows and 1024 columns. Display driver circuit 100 includes row decoder 104, write hold register 106, pointer 108, instruction decoder 110, invert logic 112, timing generator 114, and input buffers 116, 118, and 120. Driver circuit 100 receives clock signals via SCLK terminal 122, invert signals via invert (INV) terminal 124, data and addresses via 32-bit system data bus 126, and operating instructions via 2-bit op-code bus 128, all from a system (e.g., a computer) not shown. Timing generator 114 generates timing signals, by methods well known to those skilled in the art, and provides these timing signals to the components of driver circuit 100, via clock signal lines (not shown), to coordinate the operation of each of the components.
Invert logic 112 receives the invert signals from the system via INV terminal 124 and buffer 116, and receives the data and addresses from the system via system data bus 126 and buffer 118. Responsive to a first invert signal ( ), invert logic 112 asserts the received data and addresses on a 32-bit internal data bus 130. Responsive to a second invert signal (INV), invert logic 112 asserts the complement of the received data on internal data bus 130. Internal data bus 130 provides the asserted data to write hold register 106, and provides the asserted row addresses (via 10 of its 32 lines) to row decoder 104.
Instruction decoder 110 receives op-code instructions from the system, via op-code bus 128 and buffer 120, and, responsive to the received instructions, provides control signals, via an internal control bus 132, to row decoder 104, write hold register 106, and pointer 108. Responsive to the system asserting data on system data bus 126 and a first instruction (i.e., Data Write) on op-code bus 128, instruction decoder 110 asserts control signals on control bus 132, causing write hold register 106 to load the asserted data via internal data bus 130 into a first portion of write hold register 106. Because internal data bus 130 is only 32 bits wide, 32 data write commands are necessary to load an entire line (1024 bits) of data into write hold register 106. Pointer 108 provides an address, via a set of lines 134, which indicates the portion of write hold register 106 to which the data is to be written. As each successive Data Write command is executed, pointer 108 increments the address asserted on lines 134 to indicate the next 32-bit portion of write hold register 106.
Responsive to the system asserting a row address on system data bus 126 and a second instruction (i.e., load row address) on op-code bus 128, instruction decoder 110 asserts control signals on control bus 132 causing row decoder 104 to store the asserted row address. Then, responsive to the system asserting a third instruction (i.e., Array Write) on op-code bus 128, instruction decoder 110 asserts control signals on control bus 132, causing write hold register 106 to assert the 1024 bits of stored data on a set of 1024 data output terminals 136, and causing row decoder 104 to decode the stored row address and assert a write signal on one of a set of 768 row enable lines 138 corresponding to the decoded row address. The write signal on the corresponding row enable line causes the data being asserted on data output terminals 136 to be latched into a corresponding row of pixel cells (not shown in FIG. 1) of pixel array 102.
FIG. 2 shows an exemplary pixel cell 200(r,c) of display 102, where (r) and (c) indicate the row and column of the pixel cell 200, respectively. Pixel cell 200 includes a latch 202, a pixel electrode 204, and switching transistors 206 and 208. Latch 202 is a static random access memory (SRAM) latch. One input of latch 202 is coupled, via transistor 206, to a Bit+ data line 210(c), and the other input of latch 202 is coupled, via transistor 208 to a Bit- data line 212(c). The gate terminals of transistors 206 and 208 are coupled to row enable line 138(r). An output terminal 214 of latch 202 is coupled to pixel electrode 204. A write signal on row enable line 138(r) places transistors 206 and 208 into a conducting state, causing the complementary data asserted on data lines 210(c) and 212(c) to be latched, such that the output terminal 214 of latch 202, and coupled pixel electrode 204, are at the same logic level as data line 210(c).
It should be noted that that the above described display driver circuit 100 is presented by way of example only, and it is not represented that this example is the only way to provide signals to the pixel array 102. However, whatever the method or apparatus used for delivering a write signal to pixel cell 200 from row decoder 104 (FIG. 1) via the row enable line 138(r), there has existed in the prior art a problem that the row enable line 138(r) is fragile and quite susceptible to flaws during the manufacturing process or thereafter. When a row enable line 138(r) fails to make a complete electrical path across the pixel array 102 (FIG. 1) a portion of a row of pixel cells 200 (r,c) will not be operable. Although this will not particularly render the assembled pixel array 102 and display driver circuit 100 entirely inoperable, it will likely result in a perceptible flaw in the perceived visual display, and is unacceptable.
It would be desirable to have a video display driver which could withstand open circuits in the lines enabling rows of the pixel array without suffering a deterioration of the video image produced thereby. However, to the inventor's knowledge no such apparatus or method has existed in the prior art.